Data communication between networks frequently involves translation between network protocols. This translation step includes examination of addressing information expressed according to a first network protocol and replacing it with addressing information expressed according to a second network protocol. This operation has typically been carried out by CISC or RISC general purpose microprocessors.
As network bandwidths have increased, data transmission rates have also increased. These increases in data transmission rates have not, however, been matched by corresponding performance increases in microprocessors. For example, within the past decade, data transmission rates have increased by a factor of 10,000, from 64 KBPS to 10 GBPS. However, in that same period, processor clock rates have increased by only a factor of 33, from 33 MHz to 1 GHz.
This growing mismatch between typical data transmission rates and processor clock rates has resulted in delays, and in some cases, data loss associated with passing data between networks characterized by different protocols. This performance mismatch is farther exacerbated in storage area networks because of the processor is then burdened with maintaining considerable state information.